Computer system that maintains system wide cache coherency during deferred communication transactions
US5682516A · kind A · utility
40Cited by
4References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 1, 1994 |
| Grant date | Oct 28, 1997 |
| Priority date | — |
| Expiry date | Mar 1, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0813
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system is disclosed having a requesting bus agent that issues a communication transaction over a bus and an addressed bus agent that defers the communication transaction to avoid high bus latency. The addressed bus agent later issues a deferred reply transaction over the bus to complete the communication transaction. Special snoop ownership and cache state transition rules maintain cache coherency and processor consistency during deferred communication transactions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.