Semiconductor device and method of manufacturing the same
US5683921A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1995 |
| Grant date | Nov 4, 1997 |
| Priority date | — |
| Expiry date | Feb 24, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/116
Abstract
A MOS transistor consists of a gate insulating film, a gate electrode, a pair of sidewall spacers on the side faces of the gate electrode, lightly doped source/drain regions, and heavily doped source/drain regions, which are located below the sidewall spacers. Between the sidewall spacers and an isolation are formed concave portions. On a silicon substrate in the concave portions are formed insulating films for capacitance reduction. On the insulating films for capacitance reduction are formed withdrawn electrodes. The heavily doped source/drain regions are electrically connected to the withdrawn electrodes between the sidewall spacers and the insulating films for capacitance reduction. Consequently, a pn junction capacitance beneath the source/drain regions is reduced, while the contact area between the source/drain regions and wiring is surely obtained, thereby achieving higher integration of the MOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.