Self-aligned source and body contact structure for high performance DMOS transistors and method of fabricating same

US5684319A · kind A · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventor

• Francois Hebert · San Mateo, US

Key dates

• Filing date: Aug 24, 1995
• Grant date: Nov 4, 1997
• Expiry date: Aug 24, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0291

Abstract

A DMOS device structure, and method of manufacturing the same features a self-aligned source and body contact structure which requires no additional masks. Polysilicon spacers are used to form the source region at the periphery of the gate polysilicon. The preferred method of manufacturing uses five masks to produce a discrete DMOS semiconductor chip. An N- epitaxial layer is grown on an N+ substrate. Thick field oxide is grown. A first mask is used to etch an active region. Thin gate oxide is grown. Doped polysilicon is then deposited. A second mask is used to etch the polysilicon, thereby forming the gates. Insulating oxide is grown. A blanket P body implantation is performed. A thermal drive-in step laterally and vertically diffuses the implanted P type impurity throughout body regions. The insulating oxide is etched. A polysilicon layer is deposited and doped. A dry etch leaves polyslicon spacers along the edges of the gates. A P+ body contact implantation is performed, thereby forming body contact regions. A final annealing step causes vertical and lateral out-diffusion of the N type dopant from the N+ spacers down into substrate to form source N+ regions which partially under…