Multilayered interconnection of semiconductor device
US5684331A · kind A · utility
15Cited by
8References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Nov 4, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multilayered interconnection of a semiconductor device includes a substrate, an underside interconnection layer formed on the substrate, an interlayer insulation film formed on the underside interconnection layer, an upperside interconnection layer formed on the interlayer insulation film, a contact hole formed through the upperside interconnection layer and into the interlayer insulation film, and a plug formed in the contact hole so that the plug contacts an upper part of the underside interconnection layer and a side of the upperside interconnection layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.