Shared floating-point registers and register port-pairing in a dual-architecture CPU
US5685009A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 1995 |
| Grant date | Nov 4, 1997 |
| Priority date | — |
| Expiry date | Nov 29, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45554
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual-instruction-set central processing unit (CPU) is capable of executing floating point instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Floating point data is transferred from a CISC program to a RISC program running on the CPU by using shared floating point registers. The architecturally-defined floating point registers in the CISC instruction set are merged or folded into some of the architecturally-defined floating point registers in the RISC architecture so that these merged registers are shared by the two instructions sets. In particular, the floating-point exception-mask and flags registers defined by each architecture are merged together so that CISC instructions and RISC instructions implicitly update the same merged flags register when executing floating point instructions. The RISC and CISC registers are folded together so that the CISC flags and RISC flags with the same function are merged to the same register bit. The floating-point data registers are also merged together, allowing a CISC program to pass floating-point data to a RISC program merely by writing one of its f…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.