Integrated circuit scribe line structures and methods for making same
US5686171A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1993 |
| Grant date | Nov 11, 1997 |
| Priority date | — |
| Expiry date | Dec 30, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24926
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.