Patent · US Expired

Method of making a self-aligned static induction transistor

US5686330A · kind A · utility

7Cited by
4References
17Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 23, 1996
Grant dateNov 11, 1997
Priority date
Expiry dateSep 23, 2016

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D30/202

Abstract

A method of fabricating self-aligned static induction transistors is disclosed. The method comprises fabricating a silicon substrate having an active area. A guard ring is formed around the active area. Source and gate regions are formed, and a self-aligned relatively deep trench in accordance with the present invention is formed over the gate regions. This is achieved by forming an oxide layer, and forming a polysilicon layer on the oxide layer. A second oxide layer is formed on the polysilicon layer which is then masked by a self-aligning mask. Trenches are etched into the source and gate regions using the self-aligning mask and gate regions are formed at the bottom of the trenches. The transistors are then processed to completion by forming gate, source and drain regions. This portion of the method comprises the steps of forming maskless self-aligned gate metallization, forming maskless self-aligned contacts to the gate metallization and filling the trench, forming source metallization, and forming a drain contact on the substrate. The method employs a single minimum geometry trench mask. The key features of the transistors are defined by the trench mask and related processing p…

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.