Power-up/power-down reset circuit for low voltage interval
US5686848A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 1996 |
| Grant date | Nov 11, 1997 |
| Priority date | — |
| Expiry date | Apr 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power up, power down reset circuit formed of charge storage apparatus for receiving and storing charge from one pole of a voltage supply, a pair of complementary field effect transistors having source-drain circuits connected in series aiding direction between the charge storage apparatus and another pole of the voltage supply, apparatus for connecting the one pole of the voltage supply to a gate of one transistor of the pair of transistors, apparatus for applying a voltage derived from the one pole of the voltage supply but having a value reduced from voltage of the voltage supply, to a gate of another transistor of the pair of transistors, and apparatus for providing a reset pulse from a junction between the source-drain circuits of the pair of transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.