Zero-crossing triac and method
US5686857A · kind A · utility
4Cited by
13References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 6, 1996 |
| Grant date | Nov 11, 1997 |
| Priority date | — |
| Expiry date | Feb 6, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/136
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A triac (100) utilizes an FET (107) to inhibit firing of a transistor (112) that forms a portion of the SCR of the triac (100). A DMOS transistor (106) is used to supply a substantially constant bias current to the transistor (107) in order to facilitate rapid turn-on of the transistor (107) around the zero-crossing of the voltage applied to the triac (100).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.