Implementation of binary floating point using hexadecimal floating point unit
US5687106A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1995 |
| Grant date | Nov 11, 1997 |
| Priority date | — |
| Expiry date | Mar 31, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system supporting multiple floating point architectures. In an embodiment of the invention, a floating point unit (FPU) is optimized for hex format. The FPU uses a hex internal dataflow with a with an exponent and bias sufficient to support a binary floating point architecture. The FPU includes format conversion means, rounding means, sticky bit calculation means, and special number control means to execute binary floating point operations according to the IEEE 754 standard. An embodiment of the invention provides a system for executing floating point operations in either IBM S/390 hexadecimal format or IEEE 754 binary format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.