Multibit single cell memory element having tapered contact
US5687112A · kind A · utility
546Cited by
2References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 19, 1996 |
| Grant date | Nov 11, 1997 |
| Priority date | — |
| Expiry date | Apr 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically operated, directly overwritable, multibit, single-cell chalcogenide memory element with multibit storage capabilities and having at least one contact for supplying electrical input signals to set the memory element to a selected resistance value, the second contact tapering to a peak adjacent to the memory element. In this manner the tapered contact helps define the size and position of a conduction path through the memory element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.