PMOS memory cell with hot electron injection programming and tunnelling erasing
US5687118A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 14, 1995 |
| Grant date | Nov 11, 1997 |
| Priority date | — |
| Expiry date | Nov 14, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A P-channel MOS memory cell has P+ source and drain regions formed in an N-well. A thin tunnel oxide is provided between the well surface and an overlying floating gate. In one embodiment, the thin tunnel oxide extends over a substantial portion of the active region and the device. An overlying control gate is insulated from the floating gate by an insulating layer. The device is programmed via hot electron injection from the drain end of the channel region to the floating gate, without avalanche breakdown, which allows the cell to be bit-selectable during programming. Erasing is accomplished by electron tunneling from the floating gate to the N-well with the source, drain, and N-well regions equally biased. Since there is no high drain/well junction bias voltage, the channel length of the cell may be reduced without incurring and destructive junction stress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.