Multi-mode cache structure
US5687131A · kind A · utility
11Cited by
1References
12Claims
0Family size
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Key dates
| Filing date | Mar 22, 1996 |
| Grant date | Nov 11, 1997 |
| Priority date | — |
| Expiry date | Mar 22, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2515
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multimode cache structure includes a predefined block of memory and controls for that block of memory which allow the memory block to perform multiple functions. The selectable, multiple functions include a cache mode, a SRAM mode, a flush mode and an invalidate mode. A control register is defined and is associated with the predefined memory block, which control register includes multiple status bits therein. Each of the status bits corresponds to one of the multiple functions and, when a particular status bit is set, the predefined block of memory performs a function corresponding to the status bit that is set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.