Multi-layer substrate structure
US5689091A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 1996 |
| Grant date | Nov 18, 1997 |
| Priority date | — |
| Expiry date | Sep 19, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-layer substrate structure and a method for fabricating the same are provided. Thin metal foils are laminated on the top and bottom sides of a non-conductive layer so as to form a laminated substrate. A plurality of plated-through holes are formed in the laminated substrate and are then filled with an epoxy. The laminated substrate is then patterned and etched. Epoxy layers are disposed on both sides of the laminated substrate. The laminated substrate is formed with a plurality of smaller plated-through holes extending through the epoxy layers and with a cavity to receive an integrated-circuit die. The through holes and the epoxy layers are metallized on both sides of the laminated substrate. The laminated substrate is patterned and etched again. A solder mask is applied on both sides of the laminated substrate so as to form selective wire bondable areas and selective solderable areas. The integrated circuit die is disposed in the center of the cavity and has a plurality of bonding pads. A plurality of bonding wires are connected between corresponding selective wire bondable areas on the laminated substrate and associated bonding pads on the die. The integrated circuit die a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.