High density trenched DMOS transistor

US5689128A · kind A · utility

Assignee

• SILICONIX INCORPORATED · US

Inventors

• Fwu-Iuan Hshieh · Saratoga, US
• Mike F. Chang · Cupertino, US
• Kuo-In Chen · Los Altos, US
• Richard K. Williams · Cupertino, US
• Mohamed N. Darwish · Campbell, US

Key dates

• Filing date: Aug 21, 1995
• Grant date: Nov 18, 1997
• Expiry date: Aug 21, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/393

Abstract

The cell density of a trenched DMOS transistor is increased by overcoming the problem of lateral diffusion of deep P+body regions. This problem is solved in three versions. In a first version, the deep P+body region is formed using a high energy implant into a single epitaxial layer. In a second version, a double epitaxial layer is used with a somewhat lower but still high energy deep P+body implant. In a third version, there is no deep P+body implant but only the double epitaxial layer is used. The cell density is improved to more than 12 million cells per square inch in each of the three versions.