Low capacitance input/output integrated circuit
US5691213A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1995 |
| Grant date | Nov 25, 1997 |
| Priority date | — |
| Expiry date | Sep 15, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
A low capacitance input/output integrated circuit and a method by which the low capacitance input/output integrated circuit is formed. Formed upon a semiconductor substrate is an input/output integrated circuit which contains a minimum of one integrated circuit device. The integrated circuit device, in turn, possesses at minimum a source electrode and a drain electrode of the same polarity. Coincident with the source electrode and the drain electrode are normally at least one ion implant of polarity opposite to the source electrode and the drain electrode. At least a portion of the drain electrode is masked when the ion implant(s) of polarity opposite to the source electrode and the drain electrode are provided into the source electrode region and the drain electrode region of the integrated circuit device(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.