Method of manufacturing a semiconductor memory device
US5691219A · kind A · utility
43Cited by
5References
45Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 13, 1995 |
| Grant date | Nov 25, 1997 |
| Priority date | — |
| Expiry date | Sep 13, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/014
Abstract
A semiconductor memory device having a semiconductor substrate, an insulating layer provided on the substrate, and a memory cell. The memory cell has a switching transistor provided on the substrate and a charge storage element in a trench made in the insulating layer. The charge storage element has a bottom electrode, a dielectric layer and a top electrode deposited one on another in the order mentioned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.