Methods for precise definition of integrated circuit chip edges

US5691248A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• John Cronin · Jericho, US
• Wayne J. Howell · Williston, US
• Howard L. Kalter · Colchester, US
• Patricia E. Marmillion · Colchester, US
• Anthony M. Palagonia · Underhill, US
• Bernadette Ann Pierson · South Hero, US
• Dennis Arthur Schmidt · South Burlington, US

Key dates

• Filing date: Jul 26, 1995
• Grant date: Nov 25, 1997
• Expiry date: Jul 26, 2015

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/977
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Integrated Circuit ("IC") chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.