Nonvolatile semiconductor memory formed with silicon-on-insulator structure
US5691552A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 24, 1995 |
| Grant date | Nov 25, 1997 |
| Priority date | — |
| Expiry date | Oct 24, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides an electrically erasable and programmable nonvolatile memory having a plurality of memory cells (M1 to M8) connected in series to each other to form a NAND type flash memory array. Each of the memory cells is constructed of a floating gate, a control gate, a source region, a drain region and a channel region. Each of the memory cells is formed in a semiconductor film (3a) formed on an insulating substrate. Further, a plurality of control transistors (T1 to T8) for transmitting a voltage applied to one end of NAND array to a selected memory cell in the selective writing mode are formed of a side wall of the semiconductor film. Each of the control transistors is connected in parallel to an associated one of the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.