Row redundancy block architecture
US5691946A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 1996 |
| Grant date | Nov 25, 1997 |
| Priority date | — |
| Expiry date | Dec 3, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/84
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Row redundancy control circuits which effectively reduce design space are arranged parallel to word direction and are arranged at the bottom of the redundancy block. This architecture change makes it possible to effectively lay out the redundancy control block by introducing (1) split-global-bus shared with local row redundancy wires, (2) half-length-one-way row redundancy-wordline-enable-signal wires which allows space saving, and (3) distributed wordline enable decoders designed to take advantage of the saved space. An illegal normal/redundancy access problem caused by the address versus timing skew has also been solved. The timing necessary for this detection is given locally by using its adjacent redundancy match detection. This allows the circuit to operate completely as an address driven circuit, resulting in fast and reliable redundancy match detection. In addition, a sample wordline enable signal (SWLE) is generated by using row redundancy match detection. One two-input OR gate allows the time at which SWLE sets sample wordline (SWL) to be the same as the time at which wordline enable (WLE) signal sets wordline (WL). The time at which SWLE sets SWL remains consistent regard…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.