Fast pipeline frame full detector
US5694056A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1996 |
| Grant date | Dec 2, 1997 |
| Priority date | — |
| Expiry date | Apr 1, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17704
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pipeline frame full detection circuit. The present invention is operable within a system that loads configuration data into an integrated circuit (IC) using a serial data stream and transfer mechanism. Configuration data is transferred into the IC in sequential frames of a specified size for a given IC. The first bit of the configuration data contains a frame full indicator. The configuration data is transferred into a shift register circuit and the last bit position(s) of the shift register circuit, in addition to being stored in the shift register circuit, are shifted along a special frame full pipeline to a control unit. The control unit, upon detecting the frame full indicator, asserts a parallel write command that causes the data of the shift register circuit to be parallel transferred to a receiving column of memory. New configuration data can then be serially shifted into the same shift register circuit after a reset signal. By shifting the frame full indicator through a pipeline, the propagation delay required for the frame full indicator to reach the control unit is significantly reduced. It is this propagation delay that limits the transfer rate of the configuration dat…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.