Memory cell and wordline driver for embedded DRAM in ASIC process
US5694355A · kind A · utility
39Cited by
2References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 23, 1997 |
| Grant date | Dec 2, 1997 |
| Priority date | — |
| Expiry date | Jan 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM charge storage structure including of a p-channel access FET in an n.sup.- doped well of a p.sup.- doped substrate, a p.sup.- channel charge storage capacitor, conductive apparatus connecting a gate of the charge storage capacitor to a drain of the FET, and apparatus for applying a boosted word line voltage to a gate of the FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.