Low profile exposed die chip carrier package
US5696666A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1995 |
| Grant date | Dec 9, 1997 |
| Priority date | — |
| Expiry date | Oct 11, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package (10) comprises a semiconductor die (12), and a substrate (14) having a through-cavity opening (22) for receiving the semiconductor die. The bottom side of the substrate has solder pads (24) arranged as a peripheral pad grid array. The semiconductor die is wire bonded (26) to the to the top side of the substrate. An encapsulant (16) seals the top surface of the semiconductor die and circuitry, and portions of the top side of the substrate. The bottom surface of the semiconductor die remains exposed to the atmosphere, eliminating moisture-related die attach delamination issues and improving heat transfer away from the semiconductor die. Furthermore, the reduced contribution of the semiconductor die to overall package height results in an ultra low profile package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.