Negative voltage level shift circuit
US5696728A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 1997 |
| Grant date | Dec 9, 1997 |
| Priority date | — |
| Expiry date | Jan 3, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A negative voltage level translator includes an output terminal which is electrically connected to a word line of the associated memory array. The voltage level of the output terminal, and thus the voltage level of the associated word line, is controlled by a cross-coupled latch. If the word line associated with the negative voltage level translator has been selected during erasing, the cross-coupled latch enters a first state which results in the output terminal being pulled to a negative erase voltage. This negative erase voltage, which may be generated by a negative charge pump, is in this manner coupled to the control gates of the array's selected memory cells to cause the erasing of such memory cells via, for instance, electron tunneling. If the word line associated with the output terminal has not been selected for erasing, the cross-coupled latch enters a second state which results in the output terminal being maintained at a floating potential. This floating potential is coupled to the control gates of un-selected memory cells and thereby precludes the erasing of such un-selected memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.