Memory paging system and method including compressed page mapping hierarchy
US5696927A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1995 |
| Grant date | Dec 9, 1997 |
| Priority date | — |
| Expiry date | Dec 21, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory paging and compression system for a computer having a memory and an execution unit includes an address mapping hierarchy, a compressed page mapping hierarchy, a translation lookaside buffer, and a compression/decompression component. The address mapping hierarchy includes page tables having page table entries which map from a first portion of virtual addresses to respective pages in physical memory. The compressed page mapping hierarchy includes compressed page tables having compressed page table entries mapping from the first portion of virtual addresses to respective compressed pages in physical memory. The translation lookaside buffer caches recently used ones of the mappings from the first portion of virtual addresses to respective pages in physical memory. The compression/decompression component includes a compression/decompression engine coupled between a memory and an execution unit for alternately compressing and decompression pages in memory in respective correspondence with spills from and loads to the translation lookaside buffer. The address mapping hierarchy and compressed page mapping hierarchy may be represented in memory and the compression/decompression co…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.