Method and apparatus for reducing delays following the execution of a branch instruction in an instruction pipeline
US5696958A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 1995 |
| Grant date | Dec 9, 1997 |
| Priority date | — |
| Expiry date | Mar 15, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipeline processor, when processing a branch instruction, initiates fetching of both the target and fall-through streams prior to execution of the branch instruction such that the number of pipeline cycles between completion of execution of the branch instruction and initiation of processing of the head instruction of the target or fall-through stream is less than the minimum number of pipeline cycles between fetching of an instruction and the execution of the instruction. At least one otherwise wasted pipeline cycle is saved by early instruction fetching and storing in a prefetch register. In some cases, two or more otherwise wasted cycles can be saved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.