Method for forming a silane based boron phosphorous silicate planarization structure
US5698473A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 1994 |
| Grant date | Dec 16, 1997 |
| Priority date | — |
| Expiry date | Mar 16, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02274
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved process is provided for forming a highly planar BPSG interlevel dielectric. The process includes using a silane based source material placed within a plasma enhanced CVD chamber. The plasma enhanced CVD chamber undergoes high energy plasma deposition by applying an RF energy exceeding 950 watts in order to minimize formation of silicon-rich intermediates upon the semiconductor substrate. Moreover, densification of the BPSG material occurs within an oxygen ambient to enhance the formation of silicon dioxide having a flow angle substantially less than lower power, non-oxygen densified processes. Still further, BPSG can, if desired, be selectively etched to form a more planarized topography or a possibly recessed topography. Selective etching is brought about by a photolithography mask used to form the underlying conductors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.