Field effect transistor device with single layer integrated metal and retained semiconductor masking
US5698900A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1996 |
| Grant date | Dec 16, 1997 |
| Priority date | — |
| Expiry date | Jul 22, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/64
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A periodic table group III-IV field-effect transistor device is described. The disclosed device uses a single metalization for ohmic and Schottky barrier contacts, permanent plural etch stop layers, employs a non-alloyed ohmic connection semiconductor layer and includes a permanent semiconductor material-comprised secondary mask element, a mask element which can be grown epitaxially during wafer fabrication to perform useful functions in both the device processing and device utilization environments. The device of the invention may be achieved with both an all optical lithographic process and a combined optical and electron beam lithographic process The disclosed device provides a field-effect transistor of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.