Efficient firm consistency support mechanisms in an out-of-order execution superscaler multiprocessor
US5699538A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1994 |
| Grant date | Dec 16, 1997 |
| Priority date | — |
| Expiry date | Dec 9, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3834
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Two processor controls for supporting efficient Firm Consistency while allowing out-of-order execution of Load instructions is provided. The Touch control operates when the processor stores a subsequent Store in a pending Store buffer while awaiting any outstanding Loads or Stores. The efficiency of the pending Store is improved by issuing a Touch of the data which pre-loads the line of data in the cache that is the subject of the store. The processor can complete out-of-order execution of a subsequently issued Load relative to a prior Load, but only to its finished state. The subsequently issued Load is not allowed to complete until the prior Load is completed. The Finished Load Cancellation control ensures that Firm Consistency is maintained by canceling any finished Loads, and subsequent instructions, when the subject of the Load is the same as an invalidation request from a multiprocessor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.