Method of multi-step reactive ion etch for patterning adjoining semiconductor metallization layers
US5700739A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 1995 |
| Grant date | Dec 23, 1997 |
| Priority date | — |
| Expiry date | Aug 3, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/441
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming patterned conductor metallization layers adjoining patterned barrier metallization layers upon semiconductor substrates. A semiconductor substrate is provided which has formed upon its surface a patterned second masking layer upon a blanket first masking layer. The patterned second masking layer is formed from a photoresist material and the blanket first masking layer is formed from a silicon oxide material, a silicon nitride material or a silicon oxynitride material. Beneath the blanket first masking layer resides a blanket multi-layer metallization stack which includes a blanket conductor metallization layer adjoining a blanket barrier metallization layer. The blanket first masking layer and the upper lying blanket metallization layer of the blanket conductor metallization layer and the blanket barrier metallization layer are successively patterned through a Reactive Ion Etch (RIE) process using as the etch mask the patterned second masking layer. The patterned second masking layer is then removed. The remaining lower lying metallization layer is then patterned through a Reactive Ion Etch (RIE) process using a patterned first masking layer and the patterned u…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.