Cross-cache-line compounding algorithm for scism processors
US5701430A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Dec 23, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A certain class of computer has been previously described which has improved performance through the analysis of instructions comprising the computer's control program and appending control information to the instructions in the form of tags. One such computer analyzes instruction cache lines as they are loaded into the cache to create the tags. A disadvantage of that design is the inability to create control information for portions of the cache line whose control tags depend on instructions in another cache line as well as the line being loaded. A method and apparatus is described herein which facilitates creation of control tags based on instructions which reside in different cache lines. The method permits a more complete analysis to be performed, thereby improving processor performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.