Method for forming a via in a semiconductor device

US5702981A · kind A · utility

Inventors

• Papu D. Maniar · Austin, US
• Roc Blumenthal · Austin, US
• Jeffrey L. Klein · Austin, US
• Wei-Jen Wu · New Taipei, TW

Key dates

• Filing date: Sep 29, 1995
• Grant date: Dec 30, 1997
• Expiry date: Sep 29, 2015

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/97
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for forming vias in a semiconductor device improves the resistance and reliability of contacts formed by use of an etch stop layer during the via formation process. An etch stop layer (40), preferably a silicon nitride or aluminum nitride layer, is deposited over conductive interconnect (34). A via (44) is etched in interlayer dielectric (42), stopping on etch stop layer (40). Etch stop layer (40) is then anisotropicly etched to expose the top of conductive interconnect (34), while maintaining a portion of the etch stop layer along a sidewall of the interconnect, and particularly along those sidewall portions which contain aluminum. A conductive plug (54) is then formed in the via, preferably using one or more barrier or glue layers (50). Formation of a tungsten plug using tungsten hexafluoride can then be performed without unwanted reactions between the tungsten source gas and the aluminum interconnect.