Method for fabricating a tub structured stacked capacitor for a DRAM cell having a central column

US5702989A · kind A · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Chen-Jong Wang · Baoshan, TW
• Mong-Song Liang · Baoshan, TW

Key dates

• Filing date: Feb 8, 1996
• Grant date: Dec 30, 1997
• Expiry date: Feb 8, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/68

Abstract

The present invention provides a method of manufacturing a tub structured stacked capacitor having a central column for a dynamic random access memory (DRAM). The method uses only two photo masks to form the capacitor and a chemical mechanical polishing process to eliminate capacitor dielectric integrity problems. A first insulating layer having a contact opening is formed on a substrate. A first polysilicon layer is formed over the first insulation layer and fills the contact hole with polysilicon. Next, the first polysilicon layer over the first insulation layer is chemically mechanically polished to a depth that at least exposes the first insulation layer thereby forming a central vertical extension. An annular trench is formed in the insulating layer surrounding the central vertical extension. A second polysilicon layer and an oxide layer are formed over the trench, the central vertical extension, and the insulation layer. The oxide layer and the second polysilicon layer are then chemically mechanically polished to a depth that at least exposes the first insulation layer thereby forming a storage electrode. A capacitor dielectric layer and a top electrode are sequentially forme…