Method for forming trench transistor structure
US5705409A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 1995 |
| Grant date | Jan 6, 1998 |
| Priority date | — |
| Expiry date | Sep 28, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (12). A conductive sidewall spacer (28) is formed within the trench (24) as a gate electrode. The spacer (28) gates a first transistor (12, 28, 32) located adjacent a first half of the trench (24) and a second transistor (12, 28, 34) located adjacent a second half of the trench (24). Region (12) is a common electrode wherein the channel regions of both the first and second transistor are coupled in a serial manner through the region (12).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.