Super pipelined speculative execution vector generator
US5706420A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 6, 1995 |
| Grant date | Jan 6, 1998 |
| Priority date | — |
| Expiry date | Jun 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G1/10
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method for iterative generation of the variables used in vector generation and linear interpolation. Most significant bits are added in a last pipeline stage. Less significant bits are added in earlier pipeline stages. Breaking addition into multiple parts with each part having fewer bits to add enables a faster iterative cycle rate compared to a single long adder. Part of the vector generation algorithm requires a decision step based on the sign of the complete addition. Since this sign is generated in the last stage of the pipeline, it is not available at the time needed by earlier stages of the pipeline. Therefore, all possible combinations of outcomes for earlier pipeline stages are simultaneously speculatively computed for use by following pipeline stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.