Insulated gate semiconductor device and fabrication method therefor
US5708286A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 1996 |
| Grant date | Jan 13, 1998 |
| Priority date | — |
| Expiry date | Mar 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/611
Abstract
A vertical semiconductor device having an insulated gate structure makes use of a double-gate structure. The double-gate structure dramatically reduces the channel resistance, JFET resistance, and epitaxial resistance of the on-resistance of the power MOSFET, and implements an adequate breakdown voltage due to the effect of gate bias. In principle, a first gate and second gate having mutually facing portions are driven synchronously. This causes first and second channels to be formed in correspondence with first and second gates, and the currents flowing through these first and second channels form the on-current for this power device having a vertical structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.