Dynamic selection control in a memory
US5708604A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1997 |
| Grant date | Jan 13, 1998 |
| Priority date | — |
| Expiry date | Jan 27, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A driving circuit for a final decoding stage of an EPROM, EEPROM or FLASH EPROM for battery powered apparatuses functioning at relatively low supply voltage avoids energy absorption from a commonly boosted voltage node by switching the capacitance of the control node of the p-channel pull-up device of the CMOS inverter that drives the memory line and which constitutes the load of the driving circuit. The node is effectively charged by drawing current from the supply node and is discharged rapidly by switching in parallel thereto a previously discharged capacitance. This charge-sharing switcheable capacitance may advantageously be the capacitance of a similar p-channel pull-up control node of a deselected wordline of the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.