High performance redundancy in an integrated memory system
US5708613A · kind A · utility
4Cited by
18References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1996 |
| Grant date | Jan 13, 1998 |
| Priority date | — |
| Expiry date | Jul 22, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The preferred embodiment of the present invention provides a memory system for use in a computer system that improves the performance of a bit redundancy steering mechanism. The preferred embodiment provides a timing signal path to the bit steering mechanism with a delay shorter than that to the memory data array. Additionally, the required address signals are provided to the bit steering mechanism before the addresses are provided to the memory data array. This is preferably accomplished by bypassing the buffers and providing the address signals directly to the bit steering mechanism.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.