Multi-purpose usage of transaction backoff and bus architecture supporting same
US5708794A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 1996 |
| Grant date | Jan 13, 1998 |
| Priority date | — |
| Expiry date | Aug 5, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital processor system is disclosed that employs a bus bridge interfacing a primary bus to a secondary bus and which includes a transaction backoff signal line that provides an economical method of providing split transactions between the busses, of preventing deadlock situations between the busses, and of providing strong lock ordering across the busses. A primary bus master is backed-off the bus if it is attempting to access a device resident on the secondary bus and if mastership of the secondary bus cannot be attained by the bus bridge within a certain latency. The bus bridge further implements a method of prefetching read data from a device resident on the secondary bus in response to a primary bus master being backed-off the primary bus during a read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.