Method of forming a solderless electrical connection with a wirebond chip
US5709336A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 1996 |
| Grant date | Jan 20, 1998 |
| Priority date | — |
| Expiry date | May 31, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/4913
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dendrite surface is provided on each of the electrical contacts of a substrate, such as a test board, chip carrier, or printed wiring board. The electrical contacts on the substrate are arranged in a mirror image of the input/output pads on a wirebond chip from which the wire leads have been removed from, or not initially provided on, each of the input/output pads. The wirebond chip is aligned with the substrate, and the respective contact brought into electrical communication with each other. The wirebond chip may be removed after testing or other temporary attachment purpose, or permanently encapsulated with at least a portion of the substrate in a permanent assembly. The present invention permits wirebond chips to be selectively attached temporarily or permanently, i.e., have a pluggable capability, as well as the ability to allow a full array of I/O pad design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.