Anthony P. Ingraham
23Patents
16h-index
51Co-inventors
80Inventor score
Filing activity: Oct 30, 1990 → May 3, 2000
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5926369A | Vertically integrated multi-chip circuit package with heat-sink support | Electricity | 125 | Expired |
| US5137461A | Separable electrical connection technology | Emerging Cross-Sectional Technologies | 100 | Expired |
| US5420520A | Method and apparatus for testing of integrated circuit chips | Physics | 92 | Expired |
| US5185073A | Method of fabricating nendritic materials | Electricity | 86 | Expired |
| US6061245A | Free standing, three dimensional, multi-chip, carrier package with air flow baffle | Electricity | 64 | Expired |
| US5528159A | Method and apparatus for testing integrated circuit chips | Physics | 51 | Expired |
| US5523696A | Method and apparatus for testing integrated circuit chips | Physics | 51 | Expired |
| US6121069A | Interconnect structure for joining a chip to a circuit card | Emerging Cross-Sectional Technologies | 49 | Expired |
| US5949246A | Test head for applying signals in a burn-in test of an integrated circuit | Physics | 46 | Expired |
| US5391514A | Low temperature ternary C4 flip chip bonding method | Electricity | 43 | Expired |
| US6075287A | Integrated, multi-chip, thermally conductive packaging device and methodology | Electricity | 41 | Expired |
| US6094060A | Test head for applying signals in a burn-in test of an integrated circuit | Physics | 32 | Expired |
| US6094059A | Apparatus and method for burn-in/testing of integrated circuit devices | Physics | 31 | Expired |
| US5953623A | Ball limiting metal mask and tin enrichment of high melting point solder for low temperature interconnection | Emerging Cross-Sectional Technologies | 31 | Expired |
| US5940729A | Method of planarizing a curved substrate and resulting structure | Electricity | 21 | Expired |
| US5672980A | Method and apparatus for testing integrated circuit chips | Physics | 21 | Expired |
| US5759046A | Dendritic interconnection system | Electricity | 13 | Expired |
| US6414509B1 | Method and apparatus for in-situ testing of integrated circuit chips | Electricity | 10 | Expired |
| US6256203A | Free standing, three dimensional, multi-chip, carrier package with air flow baffle | Electricity | 10 | Expired |
| US6150255A | Method of planarizing a curved substrate and resulting structure | Electricity | 9 | Expired |
| US5709336A | Method of forming a solderless electrical connection with a wirebond chip | Emerging Cross-Sectional Technologies | 7 | Expired |
| US5994910A | Apparatus, and corresponding method, for stress testing wire bond-type semi-conductor chips | Physics | 5 | Expired |
| US5659256A | Method and apparatus for testing integrated circuit chips | Physics | 3 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.