Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells

US5710072A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Wolfgang Krautschneider · Ottobrunn, DE
• Lothar Risch · Neubiberg, DE
• Franz Hofmann · Munich, DE

Key dates

• Filing date: Nov 18, 1996
• Grant date: Jan 20, 1998
• Expiry date: Nov 18, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/811

Abstract

To produce an arrangement containing self-amplifying dynamic MOS transistor memory cells which each comprise a selection transistor, a memory transistor and a diode structure, the selection transistor and the memory transistor being connected in series via a common nodal point and the diode structure being connected between the common nodal point and the gate electrode (10) of the memory transistor, the selection transistor and the memory transistor are formed as vertical MOS transistors. For this purpose a vertical sequence of suitably doped zones (2, 3, 4) in which trenches (5, 6) are produced and which are provided with gate dielectric (7, 8) and gate electrode (9, 10) is produced, in particular, by LPCVD epitaxy or by molecular-beam epitaxy.