Tungsten silicide polycide gate electrode formed through stacked amorphous silicon (SAS) multi-layer structure.
US5710454A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 29, 1996 |
| Grant date | Jan 20, 1998 |
| Priority date | — |
| Expiry date | Apr 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28061
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a tungsten silicide polycide gate electrode within a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and the tungsten silicide polycide gate electrode which is formed through the method. Formed upon a semiconductor substrate is a gate oxide layer. Formed upon the gate oxide layer is a first polysilicon layer which is formed through annealing a first amorphous silicon layer. Formed upon the first polysilicon layer is a second polysilicon layer which is formed through annealing a second amorphous silicon layer. Formed upon the second polysilicon layer is a tungsten silicide layer formed through a Chemical Vapor Deposition (CVD) method. The first polysilicon layer and the second polysilicon layer have a crystallite size no greater than about 0.3 microns, and the first polysilicon layer and the second polysilicon layer have a dopant concentration larger than about 1E16 atoms per cubic centimeter. Optionally, at least a third polysilicon layer may be added through annealing at least a third amorphous silicon layer between the second polysilicon layer and the tungsten silicide layer. Optionally, an fourth amorphous silicon layer may be added directly bene…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.