Reading circuit for memory cells
US5710739A · kind A · utility
15Cited by
5References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1995 |
| Grant date | Jan 20, 1998 |
| Priority date | — |
| Expiry date | Jun 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read circuit for memory cells which has two legs, each having, in cascade with one another, an electronic switch (SW1,SW2), an active element (T1,T2), feedback connected to the active element in the other leg to jointly produce a voltage amplifier, and a switch load element (L1,L2). Each active element is driven through a high-impedance input circuit element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.