Paolo Rolandi
72Patents
13h-index
18Co-inventors
81Inventor score
Filing activity: Apr 26, 1991 → Dec 19, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7274594B2 | Non-volatile memory electronic device with NAND structure being monolithically integrated on semiconductor | Emerging Cross-Sectional Technologies | 51 | Expired |
| US5859795A | Multi-level memory circuits and corresponding reading and writing methods | Physics | 37 | Expired |
| US5999445A | Multilevel non-volatile memory devices | Physics | 31 | Expired |
| US6009041A | Method and circuit for trimming the internal timing conditions of a semiconductor memory device | Physics | 27 | Expired |
| US5179300A | Data output stage having feedback loops to precharge the output node | Electricity | 24 | Expired |
| US6198660A | Synchronous multilevel non-volatile memory and related reading method | Physics | 21 | Expired |
| US6816407B2 | Method for storing and reading data in a multilevel nonvolatile memory, and architecture therefor | Physics | 19 | Expired |
| US5923975A | Fabrication of natural transistors in a nonvolatile memory process | Electricity | 18 | Expired |
| US6525961B2 | Method and circuit for programming a multilevel non-volatile memory | Physics | 18 | Expired |
| US5267202A | Reading device for EPROM memory cells with the operational field independent of the threshold jump of the written cells with respect to the virgin cells | Physics | 17 | Expired |
| US5973966A | Reading circuit for semiconductor memory cells | Physics | 15 | Expired |
| US5710739A | Reading circuit for memory cells | Physics | 15 | Expired |
| US5659498A | Unbalanced latch and fuse circuit including the same | Electricity | 13 | Expired |
| US7417900B2 | Method and system for refreshing a memory device during reading thereof | Physics | 13 | Active |
| US6101121A | Multi-level memory circuit with regulated reading voltage | Physics | 12 | Expired |
| US5696716A | Programmable memory element | Physics | 11 | Expired |
| US6363015B1 | Reading method for non-volatile memories with sensing ratio variable with the reading voltage, and device to realize said method | Physics | 10 | Expired |
| US7075844B2 | Parallel sense amplifier with mirroring of the current to be measured into each reference branch | Physics | 10 | Expired |
| US8630115B2 | Non-volatile electronic memory device with NAND structure being monolithically integrated on semiconductor | Emerging Cross-Sectional Technologies | 10 | Active |
| US6605985B2 | High-efficiency power charge pump supplying high DC output currents | Electricity | 9 | Expired |
| US5883837A | Reading circuit for semiconductor memory cells | Physics | 8 | Expired |
| US6097628A | Multi-level memory circuit with regulated writing voltage | Physics | 8 | Expired |
| US7295472B2 | Integrated electronic non-volatile memory device having nand structure | Emerging Cross-Sectional Technologies | 8 | Expired |
| US6016271A | Method and circuit for generating a gate voltage in non-volatile memory devices | Physics | 7 | Expired |
| US6507517B2 | Circuital structure for programming data in a non-volatile memory device | Physics | 7 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.