Instruction dependency chain indentifier
US5710902A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 1995 |
| Grant date | Jan 20, 1998 |
| Priority date | — |
| Expiry date | Sep 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3838
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for identifying a sequence of instructions that generate data used by an instruction in a programmed flow of instructions includes a bit array of i lines, where i is an integer, each line representing an instruction in an ordered sequence of instructions. A line in the bit array is made up of a string of bits in which a bit position is set corresponding to a preceding instruction that the instruction is dependent upon. Logic coupled to the bit array generates the string of bits for the next instruction by setting bit positions which correspond to directly dependent instructions and additional bit positions corresponding to the predecessor instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.