Gad Sheaffer
91Patents
16h-index
89Co-inventors
87Inventor score
Filing activity: Sep 6, 1995 → Apr 3, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5710902A | Instruction dependency chain indentifier | Physics | 96 | Expired |
| US7437581B2 | Method and apparatus for varying energy per instruction according to the amount of available parallelism | Emerging Cross-Sectional Technologies | 94 | Expired |
| US8095824B2 | Performing mode switching in an unbounded transactional memory (UTM) system | Physics | 68 | Active |
| US5790822A | Method and apparatus for providing a re-ordered instruction cache in a pipelined microprocessor | Physics | 52 | Expired |
| US5909573A | Method of branch prediction using loop counters | Physics | 49 | Expired |
| US6055630A | System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units | Physics | 48 | Expired |
| US6715064B1 | Method and apparatus for performing sequential executions of elements in cooperation with a transform | Physics | 43 | Expired |
| US8407425B2 | Obscuring memory access patterns in conjunction with deadlock detection or avoidance | Physics | 42 | Active |
| US6957321B2 | Instruction set extension using operand bearing NOP instructions | Physics | 36 | Expired |
| US6594754B1 | Mapping destination logical register to physical register storing immediate or renamed source register of move instruction and using mapping counters | Physics | 28 | Expired |
| US7587584B2 | Mechanism to exploit synchronization overhead to improve multithreaded performance | Physics | 26 | Expired |
| US8250331B2 | Operating system virtual memory management for hardware transactional memory | Physics | 22 | Active |
| US8209689B2 | Live lock free priority scheme for memory transactions in transactional memory | Physics | 22 | Active |
| US6105124A | Method and apparatus for merging binary translated basic blocks of instructions | Physics | 22 | Expired |
| US5838941A | Out-of-order superscalar microprocessor with a renaming device that maps instructions from memory to registers | Physics | 21 | Expired |
| US6470444B1 | Method and apparatus for dividing a store operation into pre-fetch and store micro-operations | Physics | 19 | Expired |
| US5784307A | Division algorithm for floating point or integer numbers | Physics | 15 | Expired |
| US8161247B2 | Wait loss synchronization | Physics | 15 | Active |
| US7454601B2 | N-wide add-compare-select instruction | Physics | 14 | Expired |
| US5818745A | Computer for performing non-restoring division | Physics | 14 | Expired |
| US8886894B2 | Mechanisms to accelerate transactions using buffered stores | Physics | 13 | Active |
| US6539471B2 | Method and apparatus for pre-processing instructions for a processor | Physics | 12 | Expired |
| US8402218B2 | Efficient garbage collection and exception handling in a hardware accelerated transactional memory system | Physics | 11 | Active |
| US9785462B2 | Registering a user-handler in hardware for transactional memory event handling | Physics | 10 | Active |
| US8516201B2 | Protecting private data from cache attacks | Physics | 10 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.