Method for forming shallow trench isolation
US5712185A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 1996 |
| Grant date | Jan 27, 1998 |
| Priority date | — |
| Expiry date | Apr 23, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming shallow trench isolation without a recessed edge problem is disclosed. The present invention comprises forming a pad oxide layer on a substrate. Next, a silicon nitride layer is formed on the pad oxide, and a sacrificial layer is formed on the silicon nitride layer. A photo-resist layer that defines an active region on the sacrificial layer is applied. Thereafter, the portions of the sacrificial layer, the silicon nitride layer, the pad oxide layer and the substrate are removed to form a trench. Portions of the silicon nitride layer are undercut, and a dielectric layer is formed to fill the trench. The dielectric layer is planarized until the silicon nitride layer is exposed. Finally, the silicon nitride layer and the pad oxide layer are removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.