Method for fabricating a multiple walled crown capacitor of a semiconductor device
US5712202A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 1995 |
| Grant date | Jan 27, 1998 |
| Priority date | — |
| Expiry date | Dec 27, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/014
Abstract
A method of fabricating double and multi-cylindrical storage capacitors is provided. To form a double crown capacitor, a conductive layer is formed on a multi-layer gate and insulation structure. The conductive layer includes a portion extending through a contact hole provided in the underlying insulation structure to thereby electrically connect the conductive layer with an active region of a transistor. A groove is formed in the conductive layer defining an area for a plurality of separated electrodes. First spacers are formed on the side walls of the groove. Then, the conductive layer is anisotrophically etched using the spacers as an etch mask thus forming an annular ridge around the area where the memory device is formed. The first spacers are then removed. Second and third spacers are then formed on the both sidewalls of the annular ridge. Again, the conductive layer is anisotrophically etched using the second and third spacers as an etch mask thus forming a double crown electrode from the remaining conductive layers under the second/third spacers. A capacitor dielectric layer and a top plate electrode layer are formed over the crown electrodes to complete the capacitor. The …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.