Redundancy circuit of semiconductor memory device
US5712821A · kind A · utility
4Cited by
8References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 1, 1996 |
| Grant date | Jan 27, 1998 |
| Priority date | — |
| Expiry date | Jul 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/84
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundancy circuit of a semiconductor memory device is provided, including: a plurality of repairing word lines for repairing the normal word line connected to a failed cell; a plurality of repairing paths for selecting a random repairing word line of the repairing word lines; and at least one comparing means for enabling at least two repairing word lines in case the respective paths corresponding to the same address on the normal decoding path and the repairing path are simultaneously enabled, whereby the normal word line of the failed cell is simultaneously enabled with at least two repairing word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.